HKUST's Prof. Yuan Xie and Collaborators Receive A. Richard Newton Award for Pioneering 3D-Stacked MRAM Research

August 3, 2026·
Shiyi Liu
Shiyi Liu
· 7 min read
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Prof. Yuan Xie of the Hong Kong University of Science and Technology (HKUST) and five co-authors received the 2026 A. Richard Newton Technical Impact Award in Electronic Design Automation during the opening ceremony of the 63rd Design Automation Conference (DAC), held July 26–29 in Long Beach, California.

Presented annually by the IEEE Council on Electronic Design Automation (CEDA) and ACM SIGDA, the award honors an outstanding technical contribution demonstrated by a paper published at least ten years earlier. It recognizes the lasting impact of the team’s 2008 DAC paper, “Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement.”

Prof. Xie shares the award with his former doctoral students Dr. Xiangyu Dong, Dr. Xiaoxia Wu, and Dr. Guangyu Sun, as well as longtime collaborators Prof. Hai “Helen” Li and Prof. Yiran Chen of Duke University.

The Early Exploration of 3D-Integrated Computing

The award marks the culmination of a research journey that began two decades ago, when Prof. Xie was an assistant professor at Pennsylvania State University and 3D integrated circuits remained a largely exploratory idea.

In 2006, Prof. Xie and his collaborators published “Design and Management of 3D Chip Multiprocessors Using Network-in-Memory” at the International Symposium on Computer Architecture (ISCA). The work investigated a 3D chip-multiprocessor architecture that placed memory and communication resources above processor cores. It was part of an early effort to rethink how processors and memory could be integrated vertically rather than continuing to rely only on conventional two-dimensional scaling.

This architectural direction anticipated the growing industrial importance of vertically integrated processor and memory technologies. Stacked-cache products introduced many years later, including AMD’s 3D V-Cache processors, reflect the broader movement toward bringing larger memory capacity physically closer to computing cores.

When 3D Integration Met Emerging Memory

The research took a new direction when Prof. Xie met Yiran Chen and Hai Li, then researchers at Seagate Technology working on magnetic random access memory (MRAM). MRAM stores bits in magnetic states, allowing data to be retained without continuous power. In the paper’s models, it offered essentially zero cell standby leakage and substantially greater density than SRAM, though not DRAM. However, its slower and more energy-intensive writes, together with the added fabrication cost and complexity of integrating a magnetic stack with conventional CMOS, presented important challenges.

The two lines of research proved complementary. Prof. Xie’s group had been studying processor architecture and 3D integration, while Chen and Li brought expertise in emerging memory devices and circuits. Together, they explored a mixed-technology 3D architecture in which an MRAM memory layer was stacked atop CMOS processor logic, presenting it as an alternative to integrating both technologies in a single two-dimensional chip.

Prof. Xie worked with three doctoral students at Penn State—Xiangyu Dong, Guangyu Sun, and Xiaoxia Wu—alongside Chen and Li. Their collaboration crossed the conventional boundaries between devices, circuits, computer architecture, and semiconductor integration.

The 2008 DAC paper

The resulting paper was published at the 45th DAC in 2008. The team built an HSPICE-based STT-MRAM cell model, incorporated it into a modified CACTI cache model, and used SimpleScalar simulations to compare stacked MRAM organizations with SRAM- and DRAM-based alternatives. In comparable-area L2 simulations, stacked MRAM delivered IPC generally competitive with SRAM and higher than DRAM, while the modeled 16 MB MRAM L2 reduced total power by 89 percent relative to SRAM and 70 percent relative to DRAM. These results assumed that a write buffer would hide MRAM’s longer L2 write latency; the model also found writes substantially slower and more energy-intensive than reads.

At the architecture level, the authors evaluated denser L2 and L3 organizations to exploit MRAM’s non-volatility and density relative to SRAM. They also proposed mixed-technology 3D stacking as a possible way to minimize the manufacturing-cost overhead of integrating magnetic and CMOS processes on a single two-dimensional chip. The study connected circuit-level modeling with architecture-level simulation; it did not fabricate a stacked MRAM processor or quantify manufacturing savings. The authors also cautioned that MRAM at the time was not yet dense enough to serve broadly as stacked main memory.

From an Academic Frontier to an Industry Priority

Eighteen years after the paper’s publication, both MRAM and 3D integration have become important parts of the semiconductor technology landscape. Major manufacturers have brought embedded MRAM into advanced production processes, while 3D integration and heterogeneous packaging are increasingly central to the design of high-performance processors and AI accelerators.

The paper’s methodological significance extends beyond any single memory organization. It connected an STT-MRAM circuit model with cache design, processor simulation, and a 3D-integration strategy to estimate potential system-level benefits. This cross-layer approach has become increasingly relevant as conventional transistor scaling alone can no longer deliver the improvements historically associated with Moore’s Law.

In the AI and post-Moore eras, the ability to place memory closer to computation is critical to increasing bandwidth, reducing data-movement energy, and integrating technologies optimized for different functions. The evolution of 3D ICs from a research frontier into an industry priority gives the 2008 work renewed relevance.

The same cross-layer philosophy continues to guide Prof. Xie’s research at HKUST. The JC STEM Lab of Future Advanced Computing Technologies (FACT Lab), which he directs, brings together computer architecture, electronic design automation, VLSI design, emerging memory, AI accelerators, and hardware–software co-design to develop energy-efficient computing systems.

A Lasting Legacy in People

For Prof. Xie, the award also recognizes the students who helped create the work and have since become leaders in academia and industry.

Dr. Guangyu Sun is now an Associate Professor at Peking University’s Center for Energy-Efficient Computing and Applications, where his research includes energy-efficient memory architecture, edge computing, and deep-learning acceleration. Dr. Xiangyu Dong later played a central role in system software for Google’s TPU accelerators and TPU fleet before moving to Waymo, where he leads software for autonomous-driving hardware. Dr. Xiaoxia Wu has worked on advanced 3D and 2.5D system-on-chip design, hardware verification, and electronic design automation, and is now a Senior Staff Software Engineer at Synopsys.

Their paths—from doctoral students investigating an uncertain emerging technology to established contributors in processor design, AI computing, EDA, and academic research—demonstrate another form of long-term impact. The technical recognition celebrates an influential research idea; the students’ subsequent achievements reflect the equally enduring contribution of mentorship and education.

About Prof. Yuan Xie

Prof. Yuan Xie is the Fang Professor of Engineering and Chair Professor in the Department of Electronic and Computer Engineering at HKUST. He also holds a joint appointment in the Department of Computer Science and Engineering. He received his B.S. in Electronic Engineering from Tsinghua University and his M.S. and Ph.D. in Computer Engineering from Princeton University. Before joining HKUST, he held faculty positions at Pennsylvania State University and the University of California, Santa Barbara, and gained industry experience at IBM, AMD, and Alibaba Group.

Prof. Xie is a Fellow of the IEEE, ACM, and the American Association for the Advancement of Science. His honors include the NSF CAREER Award, the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, and the IEEE Circuits and Systems Society Industrial Pioneer Award. At HKUST, he directs the JC STEM Lab of Future Advanced Computing Technologies, the Institute of Integrated Circuits and Systems, and the HKUST-Intel Joint Laboratory for High-Efficiency Intelligent Computing.

About the JC STEM Lab of Future Advanced Computing Technologies

The JC STEM Lab of Future Advanced Computing Technologies (FACT Lab) at HKUST pursues fundamental advances in computer architecture, electronic design automation, VLSI design, and machine learning. Its research spans near-memory and in-memory computing, AI accelerator design, 3D integration, emerging memory technologies, and hardware–software co-design for next-generation intelligent systems.

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