Shirui Zhao

Shirui Zhao (赵士瑞) is currently a Postdoctoral Researcher in the FACT (Future Advanced Computing Technologies) Lab within the Department of Electronic and Computer Engineering at HKUST, working under the supervision of Prof. Yuan Xie. His research focuses on RISC-V–based heterogeneous multi-core architectures for emerging embodied AI applications, with an emphasis on system–architecture co-design for efficient intelligent computing.

He received his Ph.D. from MICAS Laboratories at KU Leuven under the supervision of Prof. Marian Verhelst. His doctoral research centered on hardware–algorithm co-design for Bayesian inference in probabilistic machine learning, targeting efficient and scalable on-chip inference acceleration.

During his Ph.D., he served as chip architect and led two Intel 16nm tape-outs: a RISC-V probabilistic processor and a neuro-symbolic VLIW accelerator. He has published 14 papers in leading venues including ISSCC, JSSC, CICC, DATE, FPT, and TCAS-I. His work pioneered hardware acceleration techniques for sampling-based probabilistic machine learning, including Knuth–Yao sampling, Gumbel-based methods, and log-domain computing architectures.

Prior to his Ph.D., he obtained his M.Sc. degree in Microelectronics from the University of Chinese Academy of Sciences, Beijing, in 2015, and his B.Sc. degree in Electrical and Electronics Engineering from Northwestern Polytechnical University, China.

He also serves as a reviewer for ISSCC, JSSC, TVLSI, TCAS-I, and TCAS-II.